Embodiments of the present invention relate to a non-volatile memory device and a sensing method thereof, and more specifically, to a non-volatile memory device configured to sense multi-level data using resistance variation.
Memory devices can be classified into volatile memory devices and non-volatile memory devices. The non-volatile memory device includes a non-volatile memory cell capable of preserving stored data even when not powered. For example, the non-volatile memory device may be implemented as a flash random access memory (flash RAM), a phase change random access memory (PCRAM), or the like.
The PCRAM includes a memory cell that is implemented using a phase change material such as germanium antimony tellurium (GST), wherein the GST changes to a crystalline phase or an amorphous phase if heat is applied to the GST, thereby storing data in the memory cell.
A non-volatile memory device (e.g., a magnetic memory, a phase change memory (PCM), or the like) has a data processing speed similar to that of a volatile RAM device. The non-volatile memory device also preserves data even when power is turned off.
FIGS. 1A and 1B illustrate a conventional phase change resistor (PCR) element 4.
Referring to FIGS. 1A and 1B, the PCR element 4 includes a top electrode 1, a bottom electrode 3, and a phase change material (PCM) layer 2 located between the top electrode 1 and the bottom electrode 3. If a voltage and a current are applied to the top electrode 1 and the bottom electrode 3, a current signal is provide to the PCM layer 2, and a high temperature is induced in the PCM layer 2, such that an electrical conductive status of the PCM layer 2 changes depending on the resistance.
FIGS. 2A and 2B illustrate a phase change principle of the conventional PCR element 4.
Referring to FIG. 2A, if a low current smaller than a threshold value flows in the PCR element 4, the PCM layer 2 has a temperature suitable for a crystalline phase. Therefore, the PCM layer 2 changes to the crystalline phase, which is a low-resistance phase material. As a result, a current may flow between the top electrode 1 and the bottom electrode 3.
On the other hand, as shown in FIG. 2B, if a high current greater than the threshold value flows in the PCR element 4, the PCM layer 2 has a temperature higher than a melting point. Therefore, the PCM layer 2 changes to an amorphous phase, which is a high-resistance phase material. As a result, it is difficult for the current to flow between the top electrode 1 and the bottom electrode 3.
As described above, the PCR element 4 can store data corresponding to two resistance phases as non-volatile data. For example, if the PCR element 4 has a low-resistance phase set to data ‘1’ and the PCR element 4 has a high-resistance phase set to data ‘0’, the PCR element 4 may store two logic states for data.
In addition, a phase of the PCM layer (i.e., a phase change resistive material) 2 is not changed although the phase change memory device is powered off, such that the aforementioned data can be stored as non-volatile data.
FIG. 3 illustrates a write operation of a conventional Phase Change Resistor (PCR) cell.
Referring to FIG. 3, when a current flows between the top electrode 1 and the bottom electrode 3 of the PCR element 4 for a predetermined time, heat is generated.
Assuming that a low current smaller than a threshold value flows in the PCR element 4 during the predetermined time, the PCM layer 2 has the crystalline phase formed by a low-temperature heating state, such that the PCR element 4 becomes a low-resistance element having a set state.
Otherwise, assuming that a high current greater than the threshold value flows in the PCR element 4 during the predetermined time, the PCM layer 2 has the amorphous phase formed by a high-temperature heating state, such that the PCR element 4 becomes a high-resistance element having a reset state.
By means of the aforementioned properties, in order to write data of the set state during the write operation, a low voltage is applied to the PCR element 4 for a long period of time. On the other hand, in order to write data of the reset state during the write operation, a high voltage is input to the PCR element 4 for a short period of time.
The PCR memory device outputs a sensing current to the PCR element 4 during a sensing operation, such that it can sense data written in the PCR element 4.
FIG. 4 is a detailed block diagram illustrating a current-to-voltage converter (hereinafter referred to as a current-voltage converter) of a phase change memory device according to the related art.
Referring to FIG. 4, the current-voltage converter includes a driving unit 11, a precharge unit 12, a clamping unit 13, and a clamping precharge unit 14.
A unit cell UC includes a phase change resistor (PCR) element and a diode D.
The column selection switching unit 20 selects one of a plurality of bit lines BL in response to the column selection signal LXSW. The bit line BL selected by the column selection signal LXSW is connected to a global bit line GBL.
The driving unit 11 drives a high voltage VPPSA in response to a current driving signal SAILD, such that it outputs a sensing voltage SAI.
The precharge unit 12 precharges the sensing voltage SAI with a high voltage (VPPSA) level in response to the precharge signal SAIPRE.
The clamping unit 13 clamps a voltage level of the sensing voltage SAI in response to a clamping control signal CLMBL during a sensing operation.
The clamping precharge unit 14 percharges a node SIO with a peri-voltage (VPERI) level in response to a clamping precharge signal CLMPRE.
FIG. 5 is an operation timing diagram illustrating operations of the phase change memory device shown in FIG. 4.
Referring to FIG. 5, the clamping control signal CLMBL is activated to a high level during the T1 period. Therefore, the clamping precharge unit 14 is turned on such that the node SIO is precharged with a peri-voltage (VPERI) level.
Thereafter, a current driving signal SAILD goes to a low level during the T2 period, such that the driving unit 11 is turned on. Since the driving unit 11 is turned on, the node SIO is increased to a high voltage (VPPSA) level. The clamping control signal CLMBL goes to a high level such that the clamping unit 13 is turned on. Thus, the node SIO outputs the sensing voltage SAI.
After that, during the T3 period, the precharge signal SAIPRE is deactivated to a high level such that the developing operation of data is achieved. If the precharge signal SAIPRE is deactivated to a high level, the precharge operation is ended and the sensing operation starts.
In this case, during the T1 or T2 period before the beginning of the sensing operation, the precharge signal SAIPRE is activated to a low level such that the sensing voltage SAI is precharged with a high voltage (VPPSA) level.
However, the conventional phase change memory device for performing the above-mentioned operations including the driving unit 11 further includes a precharge unit for precharging the sensing voltage SAI prior to the sensing operation. As a result, the area of the current-voltage converter of the phase change memory device is unavoidably increased.